Amir Sohail- Initial offerings include a hierarchy explorer, linter, HDL editor, signal tracer, essential tools for hardware design and verification
- Verific App Store opens July 27 as 63rd DAC begins in Long Beach, Calif.
ALAMEDA, Calif. , July 22, 2026 (ZM NEWSWIRE) — Verific Design Automation today announced the Verific App Store with a toolkit and downloadable example applications showcasing a variety of essential electronic design automation (EDA) point tools and solutions built using its Parser Platforms.
The Verfic App Store will open Monday, July 27, as the 63rd Design Automation Conference (DAC) convenes at the Long Beach Convention Center in Long Beach, Calif. Verific will offer in DAC Booth #1052 demonstrations of the new Verific App Store examples along with demonstrations of its SystemVerilog, Verilog, VHDL and UPF front-end Parser Platforms.
“We want to show how you can build really cool EDA products with our Platform,” remarks Rob Dekker, Verific’s president, founder and CTO. “In the Verific App Store, we started with a number of useful EDA point tools that are fast running, simple to license and easy to use by AI and HI (Human Intelligence) alike.”
As the leading provider of front-end platforms, Verific powers EDA with its SystemVerilog, Verilog, VHDL and UPF parser software used as the foundation for both in-house and commercially available EDA tools and flows. Applications range from synthesis and formal verification to emulation, debugging, virtual prototyping, low-power design and design-for-test tools.
Currently Available Parser Platform Apps
Example apps currently available at the Verific App Store include a hierarchy explorer, a linter, an HDL editor and a signal tracer, essential tools for hardware design and verification.
HierRTL is a Hierarchy Explorer that reports the structural hierarchy of Verilog, SystemVerilog, and VHDL designs directly from the parse tree without the need for elaboration. Engineers can visualize and navigate the hierarchical structure of their designs and understand relationships between different modules and components, making it easier to manage complex designs.
LintRTL is a Linter tool for SystemVerilog and VHDL that identifies design issues early with configurable lint rules and advanced synthesizability checks. It analyzes code for potential errors, style issues and adherence to coding standards. It helps ensure that the HDL code is clean and maintainable, reducing bugs before simulation or synthesis.
SnapRTL is an automated HDL editor used to analyze, modify and export designs while preserving the original code and formatting. It gives engineers confidence to be able to modify their designs in a specialized environment for writing and editing HDL code. SnapRTL features syntax highlighting, code completion and error detection, streamlining the coding process and improving productivity.
TraceRTL is a Signal Tracer for SystemVerilog and VHDL to improve traceability and speed debug. It monitors and analyzes signals within the design and provides insights into signal behavior during simulation, helping engineers effectively debug and optimize their designs.
Additional apps will be added in the future.
Availability and Pricing
“We will be adding more EDA point tools as we go,” says Dekker. “Currently most base products are free of charge, and we only charge a small fee for more advanced product features.”
The Verific App Store will open July 27. Tool flow developers can download the tools in the Verific Toolkit with or without being an existing Verific customer, but registration is required. New users will be asked to register with a Verific Passport account.
Basic tools are currently free, but advanced features require a monthly subscription fee. Free evaluations are available for 14 days.
The Verific App Store can be found at: https://store.verific.com/
Verific at DAC
Attendees can arrange demos or private meetings with Verific during DAC exhibit hours July 27-29 by sending email to info@verific.com.
DAC registration is open.
About Verific Design Automation
Verific Design Automation is the leading provider of SystemVerilog, Verilog, VHDL and UPF Parser Platforms that enable project groups worldwide to develop advanced electronic design automation (EDA) products quickly and cost effectively. Verific’s software serves as the front end to synthesis, formal verification, emulation, debugging, virtual prototyping, low-power design and design-for-test tools. With offices in Alameda, Calif., and Kolkata, India, Verific has shipped more than 80,000 copies of its software used by the EDA and semiconductor industry since it was founded in 1999.
Engage with Verific at:
Email: info@verific.com
Website: www.verific.com
LinkedIn: https://www.linkedin.com/company/verific-design-automation-inc/
For more information, contact:
Nanette Collins
Public Relations for Verific
nanette@nvc.com
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